EE 560L Digital System Design

Units: 4
ASIC design, FPGAs, VHDL, verilog, test benches, simulation, synthesis, timing analysis, post-synthesis simulation, FIFOs, handshaking, memory interface, PCI bus protocol, CAD tools, design lab exercises.
Prerequisite: EE 457
Instruction Mode: Lecture, Lab Required
Grading Option: Letter